--
-- VHDL Architecture Fietscomputer_lib.row_reqs.v1
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 11:02:32 16-07-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY fc_row_reqs IS
  PORT( 
  SW            : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
  deltaT_strobe : IN  STD_LOGIC;
  V_ready       : IN  STD_LOGIC;
  time_out      : IN  STD_LOGIC;
  switch_L      : IN  STD_LOGIC;
  switch_M      : IN  STD_LOGIC;
  switch_R      : IN  STD_LOGIC;
  f1Hz          : IN  STD_LOGIC;
  f10Hz         : IN  STD_LOGIC;
  f10Hz_cntr    : IN  STD_LOGIC_VECTOR(49 DOWNTO 0);
  clk           : IN  STD_LOGIC;
  rst           : IN  STD_LOGIC;
  mode          : OUT NATURAL;
  plus          : OUT STD_LOGIC; 
  minus         : OUT STD_LOGIC; 
  row_req       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END ENTITY fc_row_reqs;

--
ARCHITECTURE v1 OF fc_row_reqs IS



SIGNAL switch2 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL switch1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL switch0 : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL cntr    : NATURAL RANGE 0 TO 4; 




BEGIN
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        switch2 <=  (OTHERS => '0');
        switch1 <=  (OTHERS => '0');
        switch0 <=  (OTHERS => '0');
      ELSIF RISING_EDGE(clk) THEN
        
        IF f10Hz = '1' THEN
          switch2 <= NOT (switch_L & switch_M  & switch_R);
          switch1 <= switch2;
        END IF;
        switch0 <= switch1;
        
      END IF;
    END PROCESS;
    
    
    
    
    
    
    PROCESS(rst, clk)
      BEGIN
        IF rst = '1' THEN
          cntr <= 0;
        ELSIF RISING_EDGE(clk) THEN
          
          IF switch1(2) = '1' AND switch1(1) = '1' AND switch0(1) = '0' THEN
            IF cntr = 4 THEN
              cntr <= 0;
            ELSE
              cntr <= cntr + 1;
            END IF;
          ELSIF switch1(2) = '1' AND switch1(0) = '1' AND switch0(0) = '0' THEN
            IF cntr = 0 THEN
              cntr <= 4;
            ELSE
              cntr <= cntr - 1;
            END IF;
          END IF;
          
          
        END IF;
      END PROCESS;
      
      mode <= cntr;
      
      plus  <= '1' WHEN switch1(2) = '0' AND switch1(1) = '1' AND switch0(1) = '0' ELSE '0';
      minus <= '1' WHEN switch1(2) = '0' AND switch1(0) = '1' AND switch0(0) = '0' ELSE '0';
      
      
      
      
      
      PROCESS(rst, clk)
        BEGIN
          IF rst = '1' THEN
            row_req <=  (OTHERS => '0');
          ELSIF RISING_EDGE(clk) THEN
            
            IF SW(2) = '1' AND deltaT_strobe = '1'  THEN
              row_req(2) <= '1';
            ELSE
              row_req(2) <= '0';
            END IF;
            
            
            IF SW(3) = '1' AND V_ready = '1'  THEN
              row_req(3) <= '1';
            ELSE
              row_req(3) <= '0';
            END IF;
            
            IF SW(4) = '1' AND time_out = '1'  THEN
              row_req(4) <= '1';
            ELSE
              row_req(4) <= '0';
            END IF;
            
            IF SW(5) = '1' AND f1Hz = '1'  THEN
              row_req(5) <= '1';
            ELSE
              row_req(5) <= '0';
            END IF;
              
              IF SW(6) = '1' AND f1Hz = '1'  THEN
                row_req(6) <= '1';
              ELSE
                row_req(6) <= '0';
              END IF;
              
                      
                IF SW(7) = '1' AND f1Hz = '1'  THEN
                  row_req(7) <= '1';
                ELSE
                  row_req(7) <= '0';
                END IF;
                
                
            
            
            --            IF cntr = 2 AND f10Hz = '1' AND f10Hz_cntr = 4  THEN
            --              row_req(4) <= '1';
            --            ELSE
            --              row_req(4) <= '0';
            --            END IF;
            --            
            --            IF  cntr = 3 AND f10Hz = '1' AND f10Hz_cntr = 4  THEN
            --              row_req(5) <= '1';
            --            ELSE
            --              row_req(5) <= '0';
            --            END IF;
            --            
            --            IF cntr = 4 AND f10Hz = '1' AND f10Hz_cntr = 4  THEN
            --              row_req(6) <= '1';
            --            ELSE
            --              row_req(6) <= '0';
            --            END IF; 
            --            
            --            
          END IF;
        END PROCESS;
        
        
        
        
      END ARCHITECTURE v1;
      
      
      
      
      
      
      
      
      
      
      
      
      
      